1. Field of the Invention
The present invention relates to a DLL (Delayed Lock Loop) circuit which generates timing signals delayed by a prescribed phase with respect to an external reference clock, and a semiconductor memory device using same.
2. Description of the Related Art
In a synchronized semiconductor memory device, such as a synchronous DRAM (SDRAM) which performs high-speed operations in synchronism with a clock supplied by the system side, internal circuit operations are carried out in synchronism with the leading edge of the clock (phase: 0.degree.), for example, or at a timing delayed by a prescribed phase difference from the leading edge. In particular, in the case of an SDRAM, column type circuits are arranged in a pipeline configuration and pipeline gates provided between the plurality of pipeline circuits are opened by an internal control clock which is synchronized to the supplied clock, thereby causing the data in the memory cells to be transmitted and output.
However, recently, a DDR (double data rate) system has been proposed, which raises the data transfer rate by conducting internal pipeline operations in synchronism not only with the leading edge of the clock, but also with the trailing edge of the clock. In this DDR system, for example, the timing of internal operations is controlled by means of an internal control clock synchronized with the rise of the clock (phase difference 0.degree.), and an internal control clock synchronized with the fall of the clock (phase difference 180.degree.). Alternatively, the timing of internal operations may be controlled by means of an internal control clock which is delayed by 90.degree. from the rise of the clock, and an internal control clock which is delayed by 90.degree. from the fall of the clock (phase difference 270.degree. from the rise of the clock). In a further modification, the timing of internal operations may be controlled by means of an internal control clock which is phase delayed by A.degree. from the rise of the clock, and an internal control clock which is phase delayed by A.degree. from the fall of the clock.
In this case, it is necessary to generate internal control clocks delayed, respectively, by a phase of A.degree. and a phase of 180.degree.+A.degree. from the rise of the reference clock. A DLL circuit is known as a circuit for generating internal control clocks delayed by a prescribed phase from the rise of a reference clock. A DLL circuit comprises a phase comparing circuit which compares the phase of a first clock delayed by a prescribed phase from a reference clock with the phase of a second clock generated by a variable delay circuit to which this reference clock is supplied, and a delay control circuit which controls the amount of delay of the variable delay circuit in response to the phase difference detected by the phase comparing circuit, and it is able to generate an internal control clock delayed by a prescribed phase in the output of the variable delay circuit by controlling the delay control circuit such that there is a phase match between the rise of the first clock and the rise of the second clock.
A DLL circuit of this kind has been disclosed by the present applicant in Japanese Patent Application 8-339988 filled Dec. 19, 1996.
However, in order to generate an internal control clock which is delayed by more than 180.degree. from the rise of the reference clock, a plurality of variable delay circuits must be provided. In a DLL circuit formed by digital circuits, the variable delay circuits comprise a plurality of gates circuits, such as inverters, connected in series, and the amount of delay is controlled by controlling the number of inverters. Therefore, the total amount of jitter produced for intermediate values of the digital delay time period increases as the number of variable delay circuits increases.
If there is a large amount of jitter in the DLL circuit, the phase of the internal control clocks generated will change significantly, and it will be difficult to generate an internal control clock which accurately maintains the prescribed phase difference with respect to the reference external clock. In order to reduce jitter, the number of gates in the variable delay circuits may be increased, but this solution poses an obstacle to integration.
Therefore, an object of the present invention is to provide a DLL circuit which is capable of generating a clock having a large phase difference with respect to a reference clock, whilst producing little jitter.
A further object of the present invention is to provide a DLL circuit which is capable of generating a clock having a phase difference of more than 180.degree. with respect to an external reference clock, whilst producing little jitter.
A further object of the present invention is to provide a semiconductor memory device comprising the aforementioned DLL circuit.